Business Wire

MathWorks Announces Release of Simulink Design Verifier 2.0

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that Simulink Design Verifier now includes Polyspace analysis technology for automated error detection in ...
EDN

FPGA design and verification using Simulink

Xilinx System Generator for DSP is a MATLAB Simulink block set that facilitates system design. Targeting Xilinx FPGAs within the familiar MATLAB environment, System Generator for DSP gives you the ...
Electronic Design

Static Analysis For Graphical Programming

Mathworks's Simulink Design Verifier 2.0 (Fig. 1) incorporates static code analysis technology that is obtained when it acquired Polyspace Technologies. The Polyspace code verifiers detect and prove ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
EDN

Early Verification and Validation in Model-Based Design

This paper discusses some best practices for repeatable and exhaustive verification in the Simulink environment. It describes how early verification and validation (V&V) in Model-Based Design can ...
Electronic Design

MathWorks speeds up FPGA-in-the-loop verification

Natick, MA. MathWorks today announced new capabilities in HDL Verifier to speed up FPGA-in-the-loop (FIL) verification. The new FIL capabilities enable faster communication with the FPGA board and ...